The present invention relates generally to the field of semiconductor processing equipment and more specifically to a method for eliminating contaminants and residues from inside a vacuum exhaust line connected to a processing chamber.
During chemical vapor deposition (CVD) processing, deposition gases are released inside a processing chamber to form a thin film layer on the surface of a substrate being processed. Unwanted deposition on areas such as the walls of the processing chamber also occurs during such CVD processes. Because the residence time in the chamber of individual molecules in some deposition gases is relatively short, however, only a small portion of the molecules released into the chamber are consumed in the deposition process and deposited on either the wafer or chamber walls.
The unconsumed gas molecules are pumped out of the chamber along with partially reacted compounds and reaction byproducts through a vacuum exhaust line that is commonly referred to as the "foreline." Many of the compounds in this exhausted gas are still in highly reactive states and/or contain residues or particulate matter that can form unwanted deposits in the foreline. Given time, this deposition build-up of residue and/or particulate matter presents a problem. For example, if enough of the deposition material builds-up in the foreline, the foreline and/or its associated vacuum pump may clog if it is not appropriately cleaned. Even when periodically cleaned, matter build-up interferes with normal operation of the vacuum pump and can drastically shorten the useful life of the pump. Also, the solid matter may backwash from the foreline into the processing chamber and contaminate processing steps adversely effecting wafer yield.
As is known in the industry, it is common to remove deposition material that builds up on the interior of chamber walls with an in situ chamber clean operation. Common chamber cleaning techniques include the use of an etching gas, such as fluorine, to remove the deposited material from the chamber walls and other areas. In some processes, the etching gas is introduced into the chamber and a plasma is formed so that the etching gas reacts with and removes the deposited material from the chamber walls. Such cleaning procedures are commonly performed between deposition steps for every wafer or every n wafers.
Removal of deposition material from chamber walls is relatively straightforward in that the plasma is created within the chamber in an area proximate to the deposited material. Removal of deposition material from the foreline is more difficult because the foreline is downstream from the processing chamber. In a fixed time period, most points within the processing chamber come in contact with more of the etchant fluorine atoms than do points within the foreline. Thus, in a fixed time period, the chamber may be adequately cleaned by the clean process while residue and similar deposits remain in the foreline.
One method of attempting to adequately clean the foreline increases the duration of the clean operation. This is generally undesirable, however, because it adversely effects wafer throughput. Also, such residue build-up can be cleaned only to the extent that reactants from the clean step are exhausted into the foreline in a state that they may react with the residue in the foreline. In some systems and applications, the lifetime of the exhausted reactants is not sufficient to reach the end or even middle portions of the foreline. In these systems and applications, residue build-up in the middle or end of the foreline cannot be removed by an extra long clean step. Accordingly, there is a need for an apparatus for efficiently and thoroughly cleaning the foreline in a semiconductor processing system and a method of doing the same.
Several different devices have been designed to facilitate the cleaning of such forelines. One approach that has been employed to clean the foreline is to trap the particulate matter present in the exhaust stream before it reaches the vacuum pump by diverting gas flow into a collection chamber from which particulate matter cannot easily escape. Devices that rely on this technique provide a removable door or similar access to the collection chamber so that once a sufficient amount of material has built up within the chamber it can be easily removed. Typically, the substrate deposition system is temporarily shut off during the period in which the collection chamber is cleaned, thereby limiting or reducing wafer throughput of the system.
Another approach relies on a scrubbing system that uses plasma enhanced CVD techniques to extract reactive components in the exhaust gas as film deposits on electrode surfaces. The scrubbing system is designed to maximize the removal of reactants as a solid film and uses large surface area spiral electrodes. The spiral electrodes are contained within a removable canister that is positioned near the end of the foreline between the blower pump and mechanical pump. After a sufficient amount of solid waste has built up on the electrodes, the canisters may be removed for disposal and replacement.
Problems exist in this prior art method in that the system relies on the large surface area of the electrodes to provide an area for deposited solid matter to collect. To accommodate the large surface area of the electrodes, the system is necessarily large and bulky. Furthermore, extra expenses are incurred in the operation of this prior art scrubber system since the removable canister is a disposable product that must be replaced and properly disposed. Also, the scrubbing system is located downstream from a beginning portion of the vacuum foreline and thus does not ensure removal of powdery material or particulate matter that builds-up in this portion of the line.
Applied Materials, the assignee of the present invention, has developed a much improved method for cleaning the foreline that relies on what is sometimes referred to as a Downstream Plasma Apparatus or "DPA" for short. The DPA traps particulate matter generated from film deposition steps and converts the trapped particulate matter into volatile products that can be subsequently pumped through the foreline without clogging the vacuum pump. The conversion process relies on forming a plasma from an etchant gas in the area where the particles are trapped. Examples of different DPA devices are set forth in U.S. application Ser. No. 08/741,230, filed Oct. 30, 1996, entitled PARALLEL PLATE APPARATUS FOR IN-SITU VACUUM LINE CLEANING FOR SUBSTRATE PROCESSING EQUIPMENT and U.S. application Ser. No. 09/354,925, filed Jul. 15, 1999, entitled HEATED ELECTROSTATIC PARTICLE TRAP FOR IN-SITU VACUUM LINE CLEANING OF A SUBSTRATE PROCESSING CHAMBER.
In one typical mode of operation, the DPA plasma is formed while a chamber clean operation is being performed. Etchant gas exhausted from the substrate processing chamber during the clean process is dissociated in the DPA plasma. Constituents from the plasma then react with the particles and residue trapped within the DPA to form the volatile reaction byproducts. The 08/741,230 application states that another mode of operation, a passive mode, the DPA is left on to form a plasma during both film deposition and chamber cleaning operations.
DPA devices can be used to keep the foreline clean in a variety of film deposition processes including a silicon nitride film deposition processes that is generally known to be a particularly dirty process. A DPA device operates such that over time, trapped particles and/or residue are converted into volatile material at a rate at least equal to the rate at which the particles/residue accumulate. In this manner, the DPA keeps the foreline clean without temporarily shutting down the substrate processing system to empty particles from the DPA. Thus importantly, the use of the DPA does not decrease wafer throughput.
In order to meet the requirements for future generations of integrated circuits, new technology is constantly being developed and explored. For example, today's fabrication plants are routinely producing devices having 0.25 .mu.m and even 0.18 .mu.m feature sizes, and tomorrow's plants soon will be producing devices having even smaller geometries. In order to further reduce the size of devices on integrated circuits, the semiconductor industry has spent much time and effort developing conductive materials having low resistivity and insulation materials having a low dielectric constant. Low dielectric constant insulation films are particularly desirable for premetal dielectric (PMD) layers and intermetal dielectric (IMD) layers to reduce the RC time delay of the interconnect metalization, to prevent cross-talk between the different levels of metalization, and to reduce device power consumption.
One family of insulation films that the industry is currently working on integrating into established integrated circuit manufacturing processes includes carbon-doped silicon oxide films. One method of depositing such carbon-doped silicon oxide films includes flowing a process gas including an organosilane and ozone into a deposition chamber and heating the substrate to a temperature between 100-250.degree. C. during a film deposition step. A subsequent chamber clean step flows remotely dissociated fluorine atoms into the chamber to remove deposition material formed on the interior chamber walls. A DPA device can be connected to the chamber foreline to prevent particle build up in the vacuum pump.
Integration of such new technology into established integrated circuit manufacturing processes sometimes creates new issues or problems that need to be solved. For example, it has been found that after extended periods of operation, a sequence of deposition and clean processes such as those associated with the carbon-doped silicon oxide film just described may result in the formation of an organic polymer film within the DPA that is not etched away or otherwise removed by forming the DPA plasma during the chamber clean step. Instead, the present inventors have found that the organic material is resistant to fluorine etching.